Solid state image sensors are presently realised in two common forms:
Charge Coupled Devices and MOS diode arrays. Both forms require specialised fabrication processes to suit them for image sensing and both forms also require substantial electronic circuits external to the sensing chip in order to drive the arrays and to process the output signal. A complete sensor subsystem therefore typically requires an assembly of many components (often between 10 and 100 components to realise a simple camera function) with consequent implications of high production costs, power consumption and physical size.
Diode array sensors are commonly based on a two dimensional array of photodiodes implemented as the reverse-biased semiconductor junctions of the type normally used to form the source and drain regions of MOS transistors. A high reverse bias is applied (typically of the order of 3 volts or greater) and the diode then is electrically isolated and exposed to light or other radiation to be detected. Incident radiation increases the reverse-bias leakage current to the diode and this current is effectively integrated on the reverse-bias capacitance of the isolated junction causing a reduction in the reverse-bias potential. The use of such techniques for conversion of radiation to electronic charge and potential is well known and practiced. In particular this technique is used in MOS diode array type sensors. In these sensors a single MOS transistor controls access to the diode for the purpose of writing to the cell (that is, resetting to a high reverse-bias) and reading from it by connecting the diode to a bit-line (i.e. sense line or column line) and thence ultimately to charge-sensing circuits which convert the charge stored within the cell to an output voltage.
Typically the array is accessed in scan-line format whereby the array is read as consecutive rows, and within each row by consecutive pixels. This process is also commonly practiced and involves enabling each row of cells by a "word-line" which is connected in common to the access transistor gates of all cells in the row. Digital circuitry is used to generate and to drive the necessary pattern of word-line signals. Normally this circuitry may take the form of a shift register. As each word-line is enabled, one row of cells is connected to bit-lines and thereby to peripheral circuitry at the top of the array. Further digital circuitry produces enabling signals that control analogue switching or sense circuitry to enable the signals on consecutive bit-lines to be connected to the output. Again the shift-register function may be used to realise the digital circuitry.
In order to realise a compact array it is desirable to maintain a small cell pitch, typically 20 microns or less horizontally and vertically, although the cell aspect ratio need not be square. This small pitch poses significant design problems in realising the vertical and horizontal scan register circuit and it is also a serious constraint on the realisation of analogue sense and switching circuitry located at the top of each bit line.
For these reasons it has been conventional practice for MOS array sensors to include only a simple analogue switch (for example, a MOS pass-transistor) to enable the bit-line to be connected to a common read out line and thence to a common charge sense amplifier. The requirements of the sense amplifier in the terms of sensitivity, dynamic range and speed are quite formidable considering the small charge originally resident at the cell site within the array, that the amplifier is required to sense. The design of such an amplifier can therefore become quite sophisticated and the present common practice is to realise such an amplifier in external circuitry.
Therefore this sensing amplifier and the tenuous connection to it becomes a critical factor in limiting the performance of the sensor system.